1. Field of the Invention
The present invention relates to a comparator circuit, more particularly to a low power-consumption type comparator circuit for an analog to digital converter (hereinafter, referred as to "A/D converter) possibly to be embodied in a small computer system, such as a portable computer, a note book type computer and the like.
2. Description of the Prior Art
FIG. 1 shows a typical one of prior art comparator circuits. In FIG. 1, the prior art comparator circuit is provided to compare two input signals CS1, CS2 applied from respective input terminals 11, 12 and comprises a pre-amplifying circuit portion 10, a control circuit portion 20, a signal transfer circuit portion 30 and a distinguishing circuit portion 40. One of the two input signals is an input comparison signal CS1 and the other is an input reference signal CS2.
In detail, the pre-amplifying circuit portion 10 is provided to receive and amplify the two input signals CS1, CS2 up to a predetermined voltage gain, and has first and second transistors Q11, Q12 which serve as a differential amplifier.
The control circuit portion 20 also is provided to control an amplifying operation of the pre-amplifying circuit portion 10 in accordance with an externally applied control signal VB1 through a first control terminal 21, and has a transistor Q21 in which a gate is connected to the first control terminal 21 and a drain and a source thereof are respectively connected to a common connection point of the differential amplifier Q11, Q12 and a first voltage source VSS.
The signal transfer circuit portion 30 is provided to transmit the two input signals amplified thus to the distinguishing circuit portion 40, and comprises four transistors Q31 to Q34 which are arranged in a folded cascode form having two cascade structures. One of the two cascade structures is connected between a second voltage source VDD and one of two output terminals OUT1, OUT2 and is constituted by two PMOS transistors Q31, Q32 which are connected in series with each other, and the other of the two cascade structures is connected between the second voltage source VDD and the other of the output terminal OUT1, OUT2 and is constituted by two PMOS transistors Q33, Q34 which are connected in series with each other. In the folded cascade structure, the transistors Q31, Q33 are commonly controlled by an externally applied control signal VB2 through a second control terminal 31, and the transistors Q32, Q34 are commonly controlled by an externally applied control signal VB3 through a third control terminal 32.
The distinguishing circuit portion 40 is provided to distinguish output signals of the output terminals OUT1, OUT2 in response to a latch signal LB applied through a latch terminal 41 as a compared output signal, and comprises three transistors Q41, Q42, Q43. In the distinguishing circuit portion 40 as shown in FIG. 1, drain and source of the transistors Q42 are respectively connected to the output terminal OUT1 and the first voltage source VSS, and drain and source of the transistor Q43 are respectively connected to the output terminals OUT2 and the first voltage source VSS. The transistor Q41 has a gate which receives the latch signal LB, drain and source are respectively connected to gates of the transistors Q42, Q43.
In the prior art comparator circuit as shown in FIG. 1, one of the two input signals CS1, CS2 indicates a reference signal, and the other of the two input signals indicates an objective signal to be compared with the reference signal. Also, between each of the output terminals OUT1, OUT2 and the first voltage source VSS, capacitors CL1, CL2 are respectively connected.
FIGS. 2A to 2D are timing diagrams showing the operation of the prior art comparator circuit of FIG. 1.
Since the comparator circuit of FIG. 1 has the pre-amplifying circuit 10 composed of the differential amplifier Q11, Q12, a current difference occurs between the drains of the first and second transistors Q11, Q12 in accordance with voltage levels of the input signals CS1, CS2. Then, since the same voltage is commonly applied to the gates of the transistors Q31, Q33 of the signal transfer circuit portion 30, the same current signal flows through each drains of the transistors Q31, Q33. Accordingly, a current signal I32 flows to the source of the transistor Q32 of the signal transfer circuit portion 30. This current signal I32 has an amount of current that equals the source current I31 of the transistor Q31 subtracted by a current I11 passing through the transistor Q11 of the differential amplifier.
Similarly, a current signal I34 flows to the source of the transistor Q34 of the signal transfer circuit portion 30. The current signal I34 has an amount of current that equals the source current I32 of the transistor Q33 subtracted by a current I12 passing through the transistor Q12 of the differential amplifier.
However, when a comparing operation is not performed in the comparator circuit, i.e. during a stand-by state, the latch signal LB as shown in FIG. 2A becomes a high level or logical "1". Then, the transistor Q41 of the distinguishing circuit portion 40 is made conductive, and therefore a potential difference between the output terminals OUT1, OUT2 becomes logical "0" regardless of the voltage level of each of the input signals CS1, CS2, as shown in a time interval T1, i.e. at the time of from t0 to t1 of FIG. 2C.
If a comparing operation is performed in the comparator circuit, the latch signal LB becomes a low level or logical "0", so that the transistor Q41 of the distinguishing circuit portion is not made conductive. Then, the current signals I32, I34 of the transistors Q32, Q34 are respectively applied directly to drains of the transistors Q42, Q43. The current signals I32, I34 are different in current amount due to a potential difference between the voltage levels of the input signals CS1, CS2, as shown in FIG. 2B. At the same time, a potential difference occurs between the output terminals OUT1, OUT2 owing to a current differential of the current signals I32, I34, as shown by a time interval T2 of FIG. 2C. In FIG. 2C, a dashed line indicates a voltage of the output terminal OUT1, and a solid line indicates a voltage of the output terminal OUT2.
In the prior art comparator circuit, because the transistors Q42, Q43 are connected in a positive feedback structure, either of the transistors Q42, Q43, where a relatively great amount of current is applied through a gate terminal thereof, is increased in conductivity to be made conductive, but the other thereof is rapidly decreased to be made not conductive.
For example, if an electric potential of the output terminal OUT1 is slightly higher than that of the output terminal OUT2, the conductivity of the transistor Q43 is increased more than that of the transistor Q42. As a result, an electric potential of the output terminal OUT2 is relatively lowered in comparison with that of the output terminal OUT1, and thus the transistor Q42 is rapidly made non-conductive.
Therefore, the distinguishing circuit portion 40 with the above-mentioned positive feedback structure can determine level of the objective signal quickly even if a voltage difference between the input signals CS1, CS2 is very slight.
In addition, the prior art comparator circuit is constant in current consumption over overall time interval, but the output voltage thereof is varied at a time t1, t2, t3 or t4 as shown in FIG. 2D. By variation of the output voltage, charging and discharging operations are performed in the capacitors CL1, CL2, and thus a slight current variation occurs instantaneously at the time t1, t2, t3 or t4, as shown in FIG. 2D.
FIG. 3 is a circuit diagram showing the construction of another prior art comparator circuit with a low power-consumption.
The comparator circuit of FIG. 3 comprises a signal converting circuit portion 50 constituted by two NMOS transistors Q51, Q52 for converting each voltage of input signals CS1, CS2 into current signals I51, I52, a switching circuit portion 60 constituted by two NMOS transistors Q61, Q62 for controlling transmission of the current signals to output terminals OUT1, OUT2 in accordance with a latch signal LB, a high level holding circuit portion 70 constituted by two PMOS transistors Q71, Q72 and two capacitors C71, C72 for maintaining each voltage level of the output terminals to a logical high-state only when a latch operation is not performed, and an amplifying/determining circuit portion 80 having a positive feedback structure constituted by two PMOS transistors Q81, Q82 for amplifying the current signals and determining level of an objective signal.
In this comparator circuit, the latch signal LB is commonly connected to gates of the transistors Q61, Q62 of the switching circuit portion 60. When a latch operation is carried out, i.e. when the latch signal LB is a logical high level, the transistors Q61, Q62 all are made conductive, the current signals I51, I52 converted by the converting circuit portion 50 are supplied through the transistors Q61, Q62 of the switching circuit portion 60 to the transistors Q81, Q82 of the amplifying/determining circuit portion 80.
In addition, when a latch operation is not carried out, i.e. when the latch signal LB is a logical-low level, an electric potential of the output terminals OUT1, OUT2 is maintained at a logical high level by the high level holding circuit portion 70.
Hereinafter, operation of the comparator circuit of FIG. 3 will be described with reference to FIGS. 4A to 4D.
The comparator circuit of FIG. 3 has a different operation from the comparator circuit of FIG. 1. This is that, when the latch signal LB is a low level, the transistors Q61, Q62 for switching electrical connection of the input and output terminals are not made conductive and thus any current consumption does not occur.
In detail, when the latch signal LB is a low level, i.e. during a time interval t0-t1 of FIG. 4A, the transistors Q61, Q62 of the switching circuit portion 50 are not made conductive and all the transistors Q71, Q72 are made conductive, and therefore each of the output terminals OUT1, OUT2 has a high level in electric potential, as shown in FIG. 4C. As a result, it is seen from FIG. 4D that a current consumption becomes zero, as shown by the time interval t0-t1 of FIG. 4D.
When the latch signal LB is a high level at the time t1, the transistors Q71, Q72 are not made conductive, and thus the output terminals OUT1, OUT2 become free from a locking state of output operation. Then, the transistors Q61, Q62 all are made conductive, and thus the current signals I51, I52 occurring due to application of the input comparing signals CS1, CS2 start to be quantitatively increased, respectively.
However, since a voltage of the input comparison signal CS1 is higher than that of the reference signal CS2 at the time t1 as shown in FIG. 4B, the electric potential of the output terminal OUT1 is further lowered in comparison with that of the output terminal OUT2.
Since the transistors Q81, Q82 are connected with each other in a positive feedback structure, an electric potential difference between the two output terminals is rapidly amplified, and thus the voltage level of the input comparison signal CS1 can be determined in the circuit portion 80, as shown in FIG. 4C.
The current consumption in the comparator circuit of FIG. 3 will be described in detail below.
First, the current consumption is zero while the latch signal LB is a low level, but additional power is required in order to drive the capacitors C71, C72 serving as loads, when the level of the output signal is changed, i.e. at the time t1 or t2.
In the case where the latch signal is a high level, the transistors Q61, Q62 also are made conductive at the time t1, and then the current signals I51, I52 pass through the transistors Q51, Q52 to the second voltage source VSS as a ground. Then, the voltage of each one of output terminals OUT1, OUT2 is dropped.
The transistors Q81, Q82 also are made conductive, and current signals from the first voltage source VDD flow to the ground VSS through the transistors Q61, Q51 connected in series, and the transistors Q62, Q52 connected in series, respectively. Then, a large amount of current flows instantaneously.
On the other hand, after determining an electric potential difference between the output terminals OUT1, OUT2 just after the time t1, the electric potential of the output terminal OUT1 becomes low and that of the output terminal OUT2 becomes high. Then, since the potential of the output terminal OUT2 is high, the transistor Q81 is not made conductive, and thus a current flow is interrupted from the second voltage source VDD to the transistor Q61.
Also, since the potential of the output terminal OUT1 is low, the transistor Q82 is continuously made conductive, and thus a current signal flows from the second voltage source VDD to the ground VSS. Then, an amount of current flowing from VSS to VDD is determined by the voltage level of the input comparison signal CS2.
On the other hand, during the time interval of t1-t2, the voltage level of the input comparison signal CS2 is constant, and thus a current consumption also is constant, as shown in FIG. 4D.
During the interval of after the time t3 to just before the time t4, the transistor Q82 is not made conductive and the transistor Q81 is made conductive because the initial level of the input comparison signal CS1 is lower than that of the input comparison signal CS2. Accordingly, the amount of current flowing through the transistors Q61, Q51 is varied in accordance with the voltage level of the input comparison signal CS1.
As described above, in any one of the comparator circuits of FIGS. 1 and 3, since a current signal flows continuously therein even after the logical level of an input comparison signal is determined, power consumption can not be sufficiently reduced.
In addition, in the case where the prior art comparator circuit is embodied in an A/D convertor, the A/D converter having an 8-bit resolution requires a total of 256 comparator circuits, and thus a power-consumption in such an A/D converter can not be neglected.
Particularly, if it is necessary to embody an A/D converter in a portable system, a comparator with as low in power-consumption as possible must be embodied in such an A/D converter.